Energy-Efficient and Power-Constrained Techniques for Exascale Computing

The future of computing will be driven by constraints on power consumption. Achieving an exaflop will be limited to no more than 20 MW of power, forcing co-design innovations in both hardware and software to improve overall efficiency. On the hardware side, processor designs are shifting to many-core architectures to increase the ratio of computational power to power consumption. Research and development efforts of other hardware components, such as the memory and interconnect, further enhance energy efficiency and overall reliability. On the software side, simulation codes and parallel programming models will need modifications to adapt to the increased concurrency and other new features of future architectures. Developing power-aware runtime systems is key to fully utilizing the limited resources. In this paper, we survey the current research in energy-efficient and power-constrained techniques in software, then present an analysis of these techniques as they apply to a specific high-performance computing use case. Keywords— High-performance computing, HPC, dynamic voltage and frequency scaling, dynamic voltage scaling, dynamic concurrency throttling, DVFS, DVS, DCT, energy-efficient, power-efficient, poweraware, power-constrained